-- PRAGMA standard control signal mapping:
-- clk								=> clk
-- clk_48k							=> clk_48k
-- reset								=> reset
-- PAY ATTENTION:					RESET IS ACTIVE LOW
-- control_in	(0) 				=> reverb_enable
--					(7 downto 1) 	=> UNUSED
--
--	control_out	(3 downto 0)	<= UNUSED
-- 
-- PCM_data_in_right				=> PCM_data_in_right
-- PCM_data_in_left				=> PCM_data_in_left
-- PCM_data_out_right			<= PCM_data_out_right
-- PCM_data_out_left				<= PCM_data_out_left

library ieee;
use ieee.std_logic_signed.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity PRM_time_1 is
  port(
    clk				: in std_logic;
	 clk_48k			: in std_logic;
    reset			: in std_logic;
	 
	 control_in		: in std_logic_vector(7 downto 0);
	 control_out	: out std_logic_vector(3 downto 0);
	 
    PCM_data_in_right	: in std_logic_vector(15 downto 0);
	 PCM_data_in_left		: in std_logic_vector(15 downto 0);
    PCM_data_out_right	: out std_logic_vector(15 downto 0);
	 PCM_data_out_left	: out std_logic_vector(15 downto 0)
    );
end entity PRM_time_1;

architecture behaviour of PRM_time_1 is
	signal enable : std_logic := '0';
begin
	
	enable <= control_in(0);
	control_out <= control_in(3 downto 0);
	
	function_p: process(clk_48k, reset)
	begin
		if reset = '0' then
			PCM_data_out_left <= (others => '0');
			PCM_data_out_right <= (others => '0');
		elsif clk_48k'event and clk_48k = '0' then
			if enable = '1' then
				if PCM_data_in_left = X"8000" then		--because there is no substitute for this value
					PCM_data_out_left <= X"7FFF";		--set to max positive
				else
					PCM_data_out_left <= abs(PCM_data_in_left);
				end if;
			else
				PCM_data_out_left <= PCM_data_in_left;
				PCM_data_out_right <= PCM_data_in_right;
			end if;
		end if;
	end process;
end architecture behaviour;
